"Basic Digital Integrated Circuits", Prof. Martín Schullenberg, 20/11/99

This short course exploits fundamental theoretic concepts and analytical methods to develop models, circuit topologies, and design strategies for high performance, high frequency analog integrated circuits. The circuit level models for both bipolar junction and metal-oxide-semiconductor (MOS) transistors are reviewed and their critical elements are behaviorally related to the controllable parameters of their respective monolithic processes. The modeling focus provides a foundation for design-oriented discussions of such circuits as broadbanded lowpass amplifier cells, operational transconductors, and filters. In the process of presenting the topologies traditional to high performance amplifiers, feedback issues are discussed briefly from the viewpoints of stability problems and requisite compensation methods.

CONDUCT AND PEDAGOGY:

Lectures are given exclusively by Dr. Choma over one 4-hour session. Time subsequent to the formal course presentation can be provided by Dr. Choma to course attendees who have specific questions about any part of the lecture. Course notes are disseminated at the start of the course.

SYLLABUS

1. REVIEW OF BJT AND MOS OPERATION AND MODELS (0.5 Hour)
A. Overview Of Bipolar Transistor Action
B. BJT Circuit Level Models
   a. Ebers-Moll Model
   b. Enhanced Ebers-Moll Model
   c. Small Signal Model At Low Frequencies
   d. Small Signal Model At High Frequencies
   e. High Frequency Device And Circuit Performance Metrics
C. MOS Circuit Level Models
   a. Shichman-Hodges Model
   b. Enhanced Shichman-Hodges Model
   c. Small Signal Model At Low Frequencies
   d. Small Signal Model At High Frequencies
   e. High Frequency Device And Circuit Performance Metrics
2. CANONIC BROADBAND AMPLIFIER CELLS (2 Hours)
A. Common Emitter/Source Amplifier
   a. Dominant Miller Effect
   b. Non-Dominant Miller Effect (fT-Limited)
B. Emitter/Source Follower
   a. Dominant Pole And Dominant Zero
   b. Driving Point Input Impedance
   c. Driving Point Output Impedance
      i. Capacitive Output Impedance Case
      ii. Inductive Output Impedance Case
C. Common Base/Gate Amplifier
   a. Dominant And Non-Dominant Poles
   b. Driving Point Input Impedance
   c. Driving Point Output Impedance
D. Compound Transistor Connections
   a. Emitter/Source Follower-Common Emitter/Source Stage
   b. Common Emitter/Source-Common Base/Gate Cascode
   c. Common Emitter-Common Base Folded Cascode
   d. Common Emitter-Gilbert Cascode
   e. Common Emitter/Source-Wilson Cascode
   f. Unilateralized Differential Pair
3. OPERATIONAL TRANSCONDUCTANCE AMPLIFIER (OTA) (1.5 Hours)
A. Differential Input Transconductor 
   a. Differential Pair With Balanced Diode Loads
   b. Differential Pair With Balanced Wilson Cascodes
   c. Complementary Darlington Configuration
   d. Transconductance Tunability
B. Output Stage
   a. Cascode Current Source/Sink Configuration
   b. Cascode Wilson Source/Sink Configuration
   c. Complementary Darlington Configuration
C. Current Mode OTA
   a. Non-Unity Gain Configuration
   b. Wideband Unity Gain Configuration
   c. Biasing And Transconductance Tunability
   d. Engineering Macromodel For SPICE Analyses
D. OTA Building Block Cells
   a. Loaded Inverting Voltage Amplifier 
   b. Loaded Non-Inverting Voltage Amplifier
   c. Active Load Inverting Voltage Amplifier
   d. Tunable Resistance
   e. Impedance Converter
   f. Open Loop Integrator
   g. Balanced Differential Input/Differential Output OTA

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